Technical Field
The present disclosure relates to structures formed in an integrated circuit (IC) structure to align multiple vertical layers with each other, particularly in IC structures formed with multiple patterning techniques. More particularly, the present disclosure relates to a mark structure for aligning layers of an integrated circuit (IC) structure, and methods of forming the same.
Related Art
Integrated circuit fabrication requires forming large numbers of interconnected devices, such as transistors, resistors, capacitors, and diodes on the surface of a semiconductor substrate material. These devices are formed in part by selectively depositing and removing multiple layers of material, e.g., semiconductors, insulators, photoresists, masks, etch stop layers, and metals. The functionality and reliability of a particular IC depends at least partially on accurate vertical alignment between each of the layers. In some cases, a fabricator may use multiple patterning lithography to place some elements in closer lateral proximity with each other than may otherwise be possible through conventional manufacturing techniques.
Double patterning lithography is one type of multiple patterning lithography technology that has been in use for some time. Double patterning lithography generally involves creating shapes, e.g., one or more conductive elements for providing functional features and/or electrical connections within a device, that are within the same design layer but too close to each other to be assigned to the same mask layer. The shapes are instead assigned onto two different mask layers in order to satisfy spacing requirements specified in the design of the product. These two different mask layers are then used to create one layer of the IC. Other multiple patterning lithography options such as triple patterning lithography may use more than two masks. Accurate alignment between the multiple mask layers is therefore one of several important factors in fabrication of functional and reliable ICs.
Accurate alignment between mask layers may be accomplished by several approaches. One of these approaches includes forming one or more marking structures, such as one or more overlay marks and/or one or more alignment marks in various layers of the IC as it is being processed. During lithography, i.e., the printing of each layer in an IC structure, a fabricator may detect the location of a marking structure in each layer to determine whether multiple layers are aligned with each other. In the event that the detected marking structure in previously-formed layer is not in its anticipated position, the fabricator may adjust the relative position of the partially fabricated IC and the current mask reticle to bring the prior mask layer and the current mask reticle into proper alignment with one another before printing the next layer. In addition, following the lithography process, marking structures may be measured by a stand-alone or in-situ metrology tool to quantify the alignment of the current layer, imaged in photoresist, relative to the prior layer etched into the substrate, to detect if misaligned features are present. This overlay mark metrology data then allows a determination to be made to continue fabrication, conduct rework operations and feedback offsets, or discard a defective IC.
Typical marking structures may include several linear metal-filled trenches arranged parallel to one another within a dielectric material. The trenches may be arranged in groups where trenches within a group are in close proximity to one another, and multiple groups are arranged to form a structure for use as an overlay mark or alignment mark. The metal in these trenches is electrically isolated from the various devices, such as transistors, and may not have any function in the finished IC. Marking structures may optionally be positioned in kerf lines between individual dies on the semiconductor substrate. The effectiveness of a marking structure is at least partially dependent on the contrast between the materials and the background material of the partially fabricated IC. Higher contrast can improve the accuracy of imaging of the marking structure and thus the accuracy of final alignment between the various layers in an IC.
Conventional methods of forming marking structures may produce marking trenches with a metal fill that is not thick enough to produce good contrast against the background when imaged. Conventional methods may also produce marking trenches that lack uniformity. Weak contrast or non-uniformity can cause unreliable results when measuring alignment, resulting in defective product or leading to expensive and time-consuming re-work operations.